The invention relates to a DRAM cell circuit, that is to say a dynamic random access memory cell circuit.
At the present time, a so-called one-transistor memory cell is usually used as the memory cell of the DRAM cell circuit. Such a memory cell contains a transistor and a capacitor on which the information is stored in the form of a charge. By driving the transistor via a word line, the charge on the capacitor can be read out via a bit line. Since the charge of the capacitor drives the bit line and a signal generated by the charge should remain identifiable despite background noise, the capacitor must have a minimum capacitance. In order to attain the highest possible packing density of the DRAM cell circuit, capacitors are proposed which have surfaces of a complicated configuration or which have capacitor dielectrics made of special materials having high dielectric constants.
An alternative DRAM cell circuit avoids the high process outlay for producing capacitors with a small space requirement and a large capacitance. The reference by M. Heshami et al. xe2x80x9c250-MHz Skewed-Clock Pipelined Date Bufferxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, March 1996, 376, describes a DRAM cell circuit in which a memory cell is a dynamic gain memory cell which contains a first selection transistor, a memory transistor and a second selection transistor. The first selection transistor is connected between a first bit line and a gate electrode of the memory transistor. A gate electrode of the first selection transistor is connected to a first word line. The second selection transistor is connected between a source/drain region of the memory transistor and a second bit line. A gate electrode of the second selection transistor is connected to a second word line. A further source/drain region of the memory transistor is connected to a voltage terminal. As in the case of the one-transistor memory cell, the information is stored in the form of an electric charge. However, the electric charge does not have to drive the bit line directly, but rather is stored on the gate electrode of the memory transistor and serves only for controlling the latter, for which purpose even a very small quantity of electric charge is sufficient. In order to write an item of information to the gate electrode of the memory transistor, the first selection transistor is driven via the first word line, with the result that there is established at the gate electrode of the memory transistor a voltage which is dependent on a voltage on the first bit line, the magnitude of which in turn depends on the information to be written. In order to read out the information, the second selection transistor is driven via the second word line. Depending on the information, that is to say depending on the voltage on the gate electrode of the memory transistor, the memory transistor is in the on state or in the off state, and a current does or does not flow between the voltage terminal and the second bit line.
An EPROM is a nonvolatile memory cell circuit in which, in contrast to the DRAM cell circuit, the information does not have to be continuously refreshed again. The information is stored in the form of at least two different threshold voltages of transistors. In order to read out an item of information of one of the transistors, a voltage lying between the two threshold voltages is applied to a control gate electrode of the transistor. Depending on whether or not a current flows through the transistor, the logic value zero or one is read out. The threshold voltage of the transistor can be set by a floating gate electrode that is electrically insulated and disposed between the control gate electrode and a channel region of the transistor. To that end, a voltage drop is produced between the control gate electrode and the channel region or a source/drain region of the transistor, which causes electrons to tunnel into the or from the floating gate electrode. Different charges of the floating gate electrode lead to different threshold voltages of the transistor. Since the floating gate electrode is completely insulated, there are no leakage currents and the information does not have to be refreshed again.
The literature reference IEEE Transactions on Electron Devices, Volume 41, No. 6, June 1994, pages 926 to 930 describes a DRAM cell circuit having a p-channel writing transistor and an n-channel reading transistor which has a floating gate. The control gate electrodes of both transistors are connected to a word line. One of the source/drain terminals of the reading transistor is at a supply potential, and the other of its source/drain terminals is connected to a bit line. One of the source/drain terminals of the writing transistor is connected to the floating gate of the reading transistor, and the other is connected to the bit line.
U.S. Pat. No. 5,220,530 teaches a memory cell having an access transistor, whose gate electrode is connected to a word line, and a further transistor with a floating gate. One of the source/drain terminals of the access transistor is connected to a bit line, and the other source/drain terminal is connected to the control gate electrode of the further transistor. One of the source/drain terminals of the further transistor is connected to the bit line, and the other is connected to a supply potential.
It is accordingly an object of the invention to provide a DRAM cell circuit and a method for fabricating it that overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, which can be fabricated with a low process outlay in conjunction with a high packing density. Furthermore, the intention is to specify a method for operating the DRAM cell circuit and a method for producing the DRAM cell circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a dynamic random access memory (DRAM) cell circuit, which includes a voltage terminal, a word line, a bit line running transversely to the word line, and a plurality of memory cells. Each of the memory cells contains a memory transistor having a channel region, a control gate electrode, a floating gate electrode, a first source/drain region, and a second source drain region. A transfer transistor having a gate electrode, a first source/drain region and a second source/drain region is also part of each of the memory cells. The word line is connected to the gate electrode of the transfer transistor. A first dielectric layer is disposed between and isolates the floating gate electrode of the memory transistor from the channel region of the memory transistor, and the floating gate electrode is connected to the first source/drain region of the transfer transistor. A second dielectric layer is disposed between and isolates the control gate electrode of the memory transistor from the floating gate electrode of the memory transistor, and the control gate electrode is connected to the word line. The first source/drain region of the memory transistor is connected to the bit line, and the second source/drain region of the memory transistor and the second source/drain region of the transfer transistor are connected to the voltage terminal.
The problem is solved by a DRAM cell circuit having a plurality of memory cells, in which the memory cells each have a memory transistor and a transfer transistor. The gate electrode of the transfer transistor is connected to the word line. The memory transistor has a floating gate electrode that is isolated from the channel region of the memory transistor by the first dielectric layer and is connected to the first source/drain region of the transfer transistor. The memory transistor has a control gate electrode, which is isolated from the floating gate electrode by the second dielectric layer and is connected to the word line. The first source/drain region of the memory transistor is connected to the bit line, which runs transversely with respect to the word line. The second source/drain region of the memory transistor and the second source/drain region of the transfer transistor are connected to the voltage terminal.
A method for operating such a DRAM cell circuit is specified below, which method likewise solves the problem relating to reading and writing information.
In order to write information to the memory cell, the word line has applied to it a write voltage such that the transfer transistor is in the on state. Furthermore, during the writing of the information, the bit line has applied to it a bit line voltage which is dependent on the information to be stored, with the result that the floating gate electrode is charged with a charge which is dependent on the bit line voltage. The information is thus stored in the form of a charge on the floating gate electrode.
In order to read out the information of the memory cell, the word line has applied to it a read voltage such that a signal is generated on the bit line in a manner dependent on the charge on the floating gate electrode.
If either the logic one or the logic zero is intended to be stored on the memory cell, then the bit line voltage may, depending on the information to be stored, be such that the memory transistor is in the on state in the event of the logic one being read out, and is in the off state in the event of a logic zero being read out, or vice versa. If the memory transistor is in the on state, then a voltage change and/or a current change can be measured on the bit line. If the memory transistor is in the off state, the voltage and current of the bit line do not change. In this case, the signal on the bit line consists in the fact that nothing happens.
As an alternative, the memory transistor may be in the on state to varying degrees depending on the charge on the floating gate electrode, that is to say depending on the stored information.
The bit line voltage determines the charge on the floating gate electrode and the latter in turn determines the threshold voltage of the memory transistor. Different threshold voltages lead to different signals on the bit line during the read-out. If the threshold voltage is not exceeded by the read voltage, then the memory transistor is in the off state.
Between the writing and the reading-out of the information, the word line has applied to it a quiescent voltage such that the memory transistor and the transfer transistor are in the off state.
Since the memory cell does not have a capacitor, it is particularly simple to produce the memory cell with a small space requirement, with the result that the DRAM cell circuit has a particularly high packing density. An increased process outlay is not necessary since it is possible to dispense with complicated surfaces and special materials having high dielectric constants.
The memory cell may have just two transistors, for example, with the result that the packing density of the DRAM cell circuit according to the invention can be increased more simply than in the case of a DRAM cell circuit in which a memory cell contains three transistors.
The floating gate electrode does not really float, since the transfer transistor may have leakage currents, with the result that the charge on the floating gate electrode can vary over the course of time. As a rule, it is necessary to refresh the stored information.
Since, during writing, all the transfer transistors connected to the word line to which the write voltage is applied are in the on state, it is advantageous if the associated memory cells are programmed at the same time.
The write voltage is preferably such that the memory transistor is in the off state during writing. In this case, during writing, no current flows through the memory transistor and the power consumption is consequently lower. If the memory transistor and the transfer transistor are of the same conductivity type, then in this case the threshold voltage of the memory transistor is higher than that of the transfer transistor. The write voltage lies between the threshold voltage of the memory transistor and the threshold voltage of the transfer transistor.
The read voltage is preferably such that the transfer transistor is in the off state during read-out. The charge on the floating gate electrode thus remains essentially constant during read-out. Therefore, the signals on the bit line are more pronounced and e.g. the signal of the logic one differs more greatly from the signal of the logic zero. Since the information is lost less rapidly, the information has to be refreshed less often. If the memory transistor and the transfer transistor are of the same conductivity type, then in this case the threshold voltage of the transfer transistor is higher than the threshold voltage of the memory transistor. In this case, the read voltage lies between the threshold voltage of the transfer transistor and the threshold voltage of the memory transistor.
In order to obtain both a lower power consumption and more pronounced signals on the bit line and longer refresh times, it is advantageous if the memory transistor is of a conductivity type which is opposite a conductivity type of the transfer transistor. In this case, the write voltage can be chosen in such a way that the memory transistor is in the off state and the transfer transistor is in the on state. The read voltage can be chosen in such a way that the transfer transistor is in the off state and the memory transistor is in the on state.
By way of example, the transfer transistor is an n-channel transistor while the memory transistor is a p-channel transistor. As an alternative, the transfer transistor is a p-channel transistor and the memory transistor is an n-channel transistor.
If the transfer transistor is an n-channel transistor and the memory transistor is a p-channel transistor, then the write voltage is equal to a positive operating voltage, for example, and the read voltage is equal to zero volts, for example. The quiescent voltage is greater than zero volts and less than the operating voltage.
If the transfer transistor is a p-channel transistor and the memory transistor is an n-channel transistor, then the write voltage is equal to zero volts, for example, and the read voltage is equal to a positive operating voltage, for example. The quiescent voltage is greater than zero volts and less than the operating voltage.
The bit line voltage is dependent on the information to be stored and is equal to the operating voltage or equal to zero volts. By way of example, the bit line voltage is equal to the operating voltage if the logic one is intended to be stored, and equal to zero volts if the logic zero is intended to be stored.
In order to increase the packing density, it is advantageous if the second source/drain region of the memory transistor and the second source/drain region of the transfer transistor are connected to the same voltage terminal. As an alternative, the second source/drain region of the memory transistor is connected to a different voltage terminal than the second source/drain region of the transfer transistor.
The voltage terminal is kept at a constant potential.
If the transfer transistor is a p-channel transistor and the memory transistor is an n-channel transistor, then the voltage terminal is kept for example at a voltage lying between zero volts and the operating voltage.
A particularly high packing density is obtained if the transfer transistor is configured as a thin-film transistor. In this case, the source/drain regions and the channel region of the transfer transistor are composed of polysilicon and can be produced within a thin layer. The transfer transistor can be disposed as a thin-film transistor on parts of the memory transistor, which is disposed in the substrate, thereby producing a particularly high packing density.
In order to increase the packing density, it is advantageous if the control gate electrode corresponds to the gate electrode of the transfer transistor.
In order to increase the packing density, it is advantageous if the floating gate electrode corresponds to the first source/drain region of the transfer transistor.
By way of example, the first source/drain region, the channel region and the second source/drain region of the memory transistor are disposed next to one another in the substrate in a manner adjoining a surface of the substrate. An insulating layer is disposed on the substrate. The insulating layer has a depression, which reaches down to the channel region of the memory transistor. The first dielectric covers at least a bottom of the depression. A layer made of polysilicon is disposed on the insulating layer and covers sidewalls of the depression and the first dielectric at the bottom of the depression without filling the depression. The first source/drain region of the transfer transistor is a part of the layer made of polysilicon that is disposed on the first dielectric at the bottom of the depression. The second source/drain region of the transfer transistor is a part of the layer made of polysilicon that is disposed on the insulating layer. The channel region of the transfer transistor is a part of the layer made of polysilicon that is disposed on the sidewalls of the depression. The second dielectric is disposed on the layer made of polysilicon. The control gate electrode is disposed on the second dielectric. The transfer transistor is configured as a vertical thin-film transistor.
Such a DRAM cell circuit can be produced for example as now described. In the substrate, the first source/drain region, the channel region and the second source/drain region of the memory transistor are produced next to one another in a manner adjoining the surface of the substrate. The insulating layer is produced on the substrate, in which layer the depression is produced which reaches down to the channel region of the memory transistor. The first dielectric is produced at least on the bottom of the depression. The layer made of polysilicon is deposited in a manner doped in situ by a first conductivity type, with the result that the layer is disposed on the insulating layer, the sidewalls of the depression and the first dielectric at the bottom of the depression. The thickness of the layer made of polysilicon is such that the depression is not filled by the layer. Afterwards, an implantation essentially perpendicular to the surface of the substrate is doped with ions of a second conductivity type, opposite to the first conductivity type, with the result that the first source/drain region of the transfer transistor is produced from the layer made of polysilicon, which source/drain region is doped by the second conductivity type and is disposed on the first dielectric at the bottom of the depression. The second source/drain region of the transfer transistor is produced from the layer made of polysilicon, which source/drain region is doped by the second conductivity type and is disposed on the insulating layer. The channel region of the transfer transistor is produced from the layer made of polysilicon, which channel region is doped by the first conductivity type and is arranged on the sidewalls of the depression. Afterwards, the second dielectric is produced on the layer made of polysilicon and the control gate electrode of the memory transistor is produced over the second dielectric.
The first dielectric may be produced prior to the production of the insulating layer on the substrate. As an alternative, the first dielectric may be produced after the production of the depression. If the first dielectric is produced by the deposition of insulating material in this case, the first dielectric covers not only the bottom of the depression but also the sidewalls of the depression.
The memory transistor is driven particularly well if a length of its channel region is approximately equal to a length of the floating gate electrode at the bottom of the depression, or a length of the control gate electrode at the bottom of the depression. Since the floating gate electrode is a part of the layer made of polysilicon which does not adjoin the sidewalls of the depression, it is consequently advantageous if the depression is longer than the channel region of the memory transistor by approximately twice the thickness of the layer made of polysilicon.
In order to produce the depression in a self-aligned manner with regard to the channel region of the memory transistor, it is advantageous to produce a mask on the surface of the substrate, which mask covers at least the channel region of the memory transistor. An implantation is carried out with the aid of the mask, thereby producing the first source/drain region and the second source/drain region of the memory transistor. In this case, the mask prevents the channel region of the memory transistor from being implanted.
Afterwards, spacers are formed in a manner adjoining the mask. In order to produce the insulating layer, insulating material is deposited and removed until the mask and the spacers are uncovered. The depression is produced by removing the mask and the spacers. The length of the depression is consequently equal to the sum of the length of the mask and twice the thickness of the spacers. The thickness of the layer made of polysilicon is preferably approximately equal to the thickness of the spacers.
A particularly high packing density can be obtained if a contact to the voltage terminal at the same time makes contact with the second source/drain region of the memory transistor and the second source/drain region of the transfer transistor. To that end, at least a part of a contact hole that reaches down to the second source/drain region of the memory transistor is disposed in the insulating layer. A contact fills the contact hole in such a way that it overlaps the second source/drain region of the transfer transistor.
An intermediate oxide may be disposed over the control gate electrode. The contact hole can cut through the intermediate oxide and reach partly down to the second source/drain region of the transfer transistor and partly down to the second source/drain region of the memory transistor. In order to produce such a contact, first the layer made of polysilicon is patterned in such a way that it has, on the insulating layer, an extent which suitable for the contact-making of the second source/drain region of the transfer transistor. The intermediate oxide is applied after the production of the control gate electrode. By masked etching of the intermediate oxide and of the insulating layer selectively with respect to the layer made of polysilicon, a contact hole is produced in such a way that a part of the contact hole reaches down to the second source/drain region of the memory transistor and a further part of the contact hole reaches down to the layer made of polysilicon. Afterwards, the contact hole is filled with a contact.
In the case of an n-channel transistor, the source/drain regions thereof are n-doped. The channel region of the n-channel transistor may be p-doped, undoped or weakly n-doped. In the case of a p-channel transistor, the source/drain regions thereof are p-doped. The channel region of the p-channel transistor may be n-doped, undoped or weakly p-doped.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a DRAM cell circuit and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit the invention and within the scope and range of equivalents the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.